MOS devices refer to integrated circuits that include numerous MOS transistors. One way of increasing the integration of MOS devices is to decrease the size of the MOS transistors. Various methods for decreasing the size of MOS transistors have been proposed, such as the method for fabricating a short channel MOS transistor disclosed in, U.S. Pat. No. 6,245,619 B1. FIGS. 1, 2, and 3A are cross-sectional views illustrating the method for fabricating MOS transistors that is disclosed in U.S. Pat. No. 6,245,619.
Referring to FIG. 1, a pad oxide layer 3 and a pad nitride layer 5 are formed sequentially on a semiconductor substrate 1. The pad oxide layer 3 has a thickness of 80 Å to 200 Å. The pad nitride layer 5 and the pad oxide layer 3 are patterned, and then a gate hole 7 is formed to expose a portion of the semiconductor substrate 1.
Referring to FIG. 2, a gate oxide layer 9 is formed on the exposed portion of the semiconductor substrate 1. The gate oxide layer 9 has a thickness of 30 Å or less. A polysilicon gate 11 is formed in the gate hole 7 on the gate oxide layer 9.
As shown in FIG. 3A, the pad nitride layer 5 is then removed. Next, a thermal oxide layer 13 is formed on the surface of the polysilicon gate 11. a dielectric layer is formed on the semiconductor substrate 1 and on the thermal oxide layer 13. The dielectric layer is etched in an isotropic manner to form spacers 15 on the sidewalls of the polysilicon gate 11. Then, dopants are implanted in the semiconductor substrate 1 using the polysilicon gate 11 and the spacers 15 as an implant mask to form heavily-doped source/drain regions 17. Next, the spacers 15 are selectively removed and the semiconductor substrate 1 is implanted with impurity ions using the polysilicon gate 11 as an implant mask to form lightly-doped source/drain regions 19 on the surface of the semiconductor substrate 1 adjacent to the sidewalls of the polysilicon gate 11.
The length L of the lightly-doped source/drain regions 19 depends on the width W of the spacers 15. Thus, to decrease the length L of the lightly-doped source/drain regions 19 it may be necessary to decrease the width W of the spacers 15. However, the spacers 15 may also be used in the salicide (self-aligned silicide) process. In the salicide process, it may be necessary to increase the width W of the spacer 15 to prevent a bridge between the gate electrode and the source/drain regions. If this occurs, the on-current of the MOS transistor may decrease because the electrical resistance of the lightly-doped source/drain regions 19 increases. A MOS transistor fabricated by the salicide process is disclosed in FIG. 3B.
In the device shown in FIG. 3B, prior to forming the spacers 15, the semiconductor substrate 1 is implanted with impurity ions using the polysilicon gate 11 as an implant mask. The lightly-doped source/drain regions 19 are formed in the semiconductor substrate 1 at both sides of the polysilicon gate 11. Next, the spacers 15 are formed on the sidewalls of the gate 11. The semiconductor substrate 1 is implanted with impurity ions using the gate 11 and the spacers 15 as an implant mask to form the highly-doped source/drain regions 17. Metal silicide layers 21a and 21b are formed selectively on the upper portions of the gate 11 and the highly-doped source/drain regions 17 by a conventional salicide process. The lightly-doped source/drain regions 19 should be formed at a shallow depth to improve the short channel effect of the MOS transistor and, to reduce the leakage current between the metal silicide layer 21b and the semiconductor substrate 1.
FIGS. 4–7 are cross-sectional views illustrating a method for fabricating another prior art device. In FIGS. 4–7, the reference sign “a” indicates an NMOS transistor region and the reference “b” indicates a PMOS transistor region.
As shown in FIG. 4, a pad oxide layer 33 and a pad nitride layer 35 are formed sequentially on a semiconductor substrate 31. The pad nitride layer 35 and the pad oxide layer 33 are patterned to form a first gate pattern groove 37n on the NMOS transistor region (a) and a second gate pattern groove 37p on the PMOS transistor region (b). The first gate pattern groove 37n and the second gate pattern groove 37p each expose a portion of the semiconductor substrate 31.
Referring to FIG. 5, a gate oxide layer 39 is formed on the exposed surfaces of the semiconductor substrate 31. An undoped polysilicon layer is formed on the gate oxide layer 39. The undoped polysilicon layer is planarized until the upper part of the pad nitride layer 35 is exposed so as to form a first undoped gate pattern 41n in the first gate pattern groove 37n and a second undoped gate pattern 41p in the second gate pattern groove 37p. Next, a photoresist pattern 43 is formed on the PMOS transistor region (b). The first undoped gate pattern 41n is implanted with n-type impurity ions using ion implantation with a high dosage of around 5×1015 atoms/cm2 and an energy of 15 KeV using the photoresist pattern 43 as an implant mask. It is preferable to employ highly diffusive phosphorous ions as the n-type impurity ions to achieve homogenous doping of the first undoped gate pattern 41n. In this case, the maximum distribution of the impurity ions is at a projection range “Rp” which is about 200 Å below the upper surface of the first undoped gate pattern 41n. The phosphorous ions are distributed from the surface of the first undoped gate pattern 41n to about 500 Å below the top surface of the first undoped gate pattern 41n. The portion of the gate pattern 41n doped with phosphorous ions may be damaged by the ion implantation and changed from a polycrystalline state to an amorphous state.
As shown in FIG. 6, the photoresist pattern 43 is then removed. Next, the pad nitride layer 35 is removed to expose the sidewalls of the first gate pattern 41n and the second gate pattern 41p. The pad nitride layer 35 may be removed using a solution of phosphoric acid. The damaged part (or amorphous silicon region) of the first gate pattern 41n may also be easily removed to form a first deformed gate pattern. The first deformed gate pattern comprises an undoped polysilicon layer. This shows that it is difficult to dope the first gate pattern 41n with the phosphorous ions. The height of the second gate pattern 41p may remain unchanged.
Next, an n-type lightly-doped region 45 is formed in the semiconductor substrate 31 adjacent the sidewalls of the first deformed gate pattern and a p-type lightly-doped region 47 is formed in the semiconductor substrate 31 adjacent the sidewalls of the second gate pattern 41p. These lightly doped regions may be formed using conventional methods. Then, a first spacer 49n is formed on the sidewalls of the first deformed gate pattern and a second spacer 49p is formed on the sidewalls of the second gate pattern 41p. Ion implantations is then used to implant the semiconductor substrate in the NMOS transistor region (a) with a high dose of arsenic ions (e.g., 1×1015−5×1015 atoms/cm2), using the first deformed gate pattern and the first spacer 49n as an implant mask, to form a highly-doped n-type region 51.
The diffusivity of phosphorous ions is lower than that of arsenic ions. As a result, arsenic ions are used extensively to form shallow source/drain regions in NMOS transistors that have a short channel. In the example of FIGS. 4–7, the arsenic ions are also doped into the first deformed gate pattern to form an n-type gate electrode 41n′ in the NMOS transistor region (a). However, it may be difficult to homogenously dope the first deformed gate pattern with the arsenic ions because the lower diffusivity of the arsenic ions makes it difficult to fully diffuse the arsenic ions to the lower part of the first deformed gate pattern. As a result, the semiconductor substrate doped with arsenic ions typically is annealed at a high temperature for a long time or the height of the first undoped gate pattern 41n and the second gate pattern 41p is reduced in an effort to form a homogenous doping profile for the n-type gate electrode 41n′. However, the long-time, high-temperature annealing process also acts to increase the depth of the n-type heavily-doped regions 51 such that the short channel characteristic of the NMOS transistor may deteriorate.
Also, when the second undoped gate pattern 41p is formed thinly, it may cause problems in the formation of the PMOS transistor. Specifically, the semiconductor substrate may be implanted with boron ions (e.g., at a dose of 1×1015−5×1015 atoms/cm2) using the second undoped gate pattern 41p and the second spacer 49p as an implant mask to form a p-type heavily-doped region 53. The second undoped gate pattern 41p is also implanted with the boron ions during this process to form a p-type gate electrode 41p′. Unlike the phosphorous and arsenic ions, the boron ions can penetrate the interface between the second undoped gate pattern 41p and the gate oxide layer 39 and diffuse into the semiconductor substrate 31. Accordingly, when the thickness of the second undoped gate pattern 41p is thin, it may result in variation of the channel under the p-type gate electrode 41p′. This may cause instability in the threshold voltage characteristic of the PMOS transistor.
Referring to FIG. 7, a metal silicide layer 55 is selectively formed on the n-type gate electrode 41n′, the p-type gate electrode 41p′, the n-type heavily-doped region 51, and the p-type heavily-doped region 53 by a conventional salicide (self-aligned silicide) process followed by an annealing treatment. In the annealing process, impurity ions in the n-type gate electrode 41n′ may be depleted severely by a dopant segregation effect at the interface between the n-type gate electrode 41n′ and the metal silicide layer 55 because the n-type gate electrode 41n′ is thinner than the p-type gate electrode 41p′. Consequently, an impurity depletion region 57 may be generated in the n-type gate electrode 41n′, making the threshold voltage characteristic of the NMOS transistor unstable. The threshold voltage characteristic of the NMOS transistor may be degraded remarkably if the impurity depletion region 57 is formed adjacent to the gate oxide layer 39.